1. Field of the Invention
This invention relates to an internal voltage generator which supplies a predetermined voltage different from an external power supply voltage externally supplied thereto to an internal circuit of a semiconductor integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit device such as a semiconductor memory device in recent years does not use external power supply voltage V.sub.CC externally supplied thereto as it is, but lowers or raises it to produce a predetermined internal power supply voltage and supplies it to an internal circuit, by which the voltage is required, to achieve reduction of the power consumption and augmentation of the reliability of a device.
In a semiconductor memory device, for example, the sizes of transistors and other elements are reduced in order to increase the storage capacity or raise the access speed. However, since such reduction of the sizes of transistors and other elements makes it impossible to apply a high voltage to the transistors, a lowered voltage power supply circuit is provided in the semiconductor memory device to apply a lowered voltage lower than the external power supply voltage to the transistors.
Meanwhile, to word lines of a semiconductor memory device such as a DRAM (Dynamic RAM) or a non-volatile memory, a raised voltage must be applied which is higher than an external power supply voltage externally supplied thereto in order to secure a desired performance. Further, in a DRAM or some other device, a semiconductor substrate is sometimes biased to a negative voltage in order to secure a high charge holding characteristic. In this manner, a semiconductor memory device is required to include therein an internal voltage generator which generates various internal power supply voltages.
A conventional lowered voltage power supply circuit shown in FIG. 1 includes output transistor 101 formed from a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) for supplying a lowered voltage to an internal circuit which serves as a load, differential amplifier 102 for outputting a control voltage to control the gate voltage of output transistor 101, reference voltage generator 103 for supplying predetermined reference voltage V.sub.REF to differential amplifier 102, and phase compensating capacitor 104 interposed between an output contact of output transistor 101 and the ground potential for preventing oscillation. External power supply voltage V.sub.CC is supplied to output transistor 101 and differential amplifier 102.
Differential amplifier 102 includes transistors Q1, Q2 formed from P-channel MOSFETs having the gates connected commonly, transistors Q3, Q4 formed from N-channel MOSFETs connected in series to transistors Q1, Q2, respectively, and having the sources connected commonly, and current source 5 for supplying predetermined current to transistors Q1 to Q4. The gate and the drain of transistor Q2 are connected to each other so that transistors Q1, Q2 form a current mirror circuit and operate so as to make the current flowing between the gate and the drain of transistor Q1 and the current flowing between the gate and the drain of transistor Q2 equal to each other.
Reference voltage V.sub.REF is applied to the gate of transistor Q3, which serves as inverted input terminal 106 of differential amplifier 102, and the drain voltage of transistor Q3 which is as an output of differential amplifier 102 is applied to the gate of output transistor 101. Output voltage V.sub.INT (lowered voltage) output from the drain of output transistor 101 is fed back to the gate of transistor Q4 which serves as non-inverted input terminal 107 of differential amplifier 102.
In the lowered voltage power supply circuit having the construction described above, when output voltage V.sub.INT is lower than reference voltage V.sub.REF, for example, the voltage at node B of differential amplifier 102 rises while the voltage at node A lowers. Consequently, source-gate voltage V.sub.GS of output transistor 101 rises, and the lowered voltage power supply circuit operates in a direction in which it raises output voltage V.sub.INT. On the other hand, when output voltage V.sub.INT is higher than reference voltage V.sub.REF, since the voltage at node B of differential amplifier 102 lowers and the voltage at node A rises, source-gate voltage V.sub.GS of output transistor 101 lowers, and the lowered voltage power supply circuit operates in the other direction in which it lowers output voltage V.sub.INT. In other words, the lowered voltage power supply circuit shown in FIG. 1 controls so that output voltage V.sub.INT may become equal to reference voltage V.sub.REF.
Reference voltage generator 103 of the lowered voltage power supply circuit shown in FIG. 1 will be described in detail below with reference to the drawings.
Referring to FIG. 2, the conventional reference voltage generator includes, similarly to the lowered voltage power supply circuit shown in FIG. 1, output transistor 111 formed from a P-channel MOSFET for supplying reference voltage V.sub.REF to a load, differential amplifier 112 for outputting a control voltage to control the gate voltage of output transistor 111, phase compensating capacitor 114 interposed between an output contact of output transistor 111 and the ground potential for preventing oscillation, and trimming resistors R101, R102 serving as a voltage divider for dividing reference voltage V.sub.REF output from output transistor 111 at a predetermined ratio. External power supply voltage V.sub.CC is supplied to output transistor 111 and differential amplifier 112.
To non-inverted input terminal 117 of differential amplifier 112, a voltage obtained by dividing the output voltage of output transistor 111 by trimming resistors R101, R102. Thereupon, reference voltage V.sub.REF which depends upon comparison voltage V.sub.R applied to inverted input terminal 116 and a resistance ratio of trimming resistors R101, R102 as given by expression (1) given below is outputted from output transistor 111: EQU V.sub.REF =V.sub.R.times.(R101+R102)/R102 (1)
Comparison voltage V.sub.R applied to inverted input terminal 116 of differential amplifier 112 shown in FIG. 2 is supplied from such a circuit as shown in-FIG. 3, for example.
Referring to FIG. 3, the generator of comparison voltage V.sub.R includes two transistors Q5, Q6 formed from N-channel MOSFETs having threshold voltages different from each other and outputs a difference voltage between threshold voltages V.sub.T of transistors Q5, Q6 as comparison voltage V.sub.R.
In the generator of comparison voltage V.sub.R having the construction described, even if threshold voltages VT of transistors Q5, Q6 are varied by a variation of the ambient temperature, the variation of comparison voltage V.sub.R can be suppressed to a low value by selectively determining the sizes of transistors Q5, Q6 and the resistance values of resistors R103, R104 so that the voltage variations of threshold voltages V.sub.T offset each other.
If very small amplitude signal IN of a low frequency which corresponds to a disturbance is input to non-inverted input terminal 107 of differential amplifier 102 of the conventional lowered voltage power supply circuit shown in FIG. 1, then a signal having the same phase as input signal IN but having an amplified amplitude is output to node A which serves as an output of differential amplifier 102 as seen in FIG. 4. Here, however, it is assumed that lower output voltage V.sub.INT is disconnected from non-inverted input terminal 107 in order to facilitate understandings. At this time, signal V.sub.INT having a polarity opposite to that of input signal IN but having an amplitude further amplified than that at node A is output to the drain of output transistor 101. It is to be noted that the amplitude ratio between input signal IN and the signal appearing at node A is gain G.sub.01 of differential amplifier 102, and the amplitude ratio between the signal appearing at node A and output signal V.sub.INT is gain G.sub.02 of output transistor 101.
Then, if the frequency of input signal IN is raised, then the signal appearing at node A cannot follow up the frequency of input signal IN and the phase of the signal appearing at node A is delayed. Also the gain decreases, and the amplitude decreases when compared with that when input signal IN has the low frequency. Similarly, also output signal V.sub.INT exhibits a phase delayed further from that of the signal at node A, and the amplitude decreases when compared with that when input signal IN has the low frequency.
If the frequency of input signal IN is further raised, then the phase of output signal V.sub.INT is delayed further, and finally, the phase of output voltage V.sub.INT is delayed by 180 degrees and becomes the same phase as input signal IN. At this time, if the amplitude of output signal V.sub.INT is greater than that of input signal IN (if total gain G.sub.01 +G.sub.02 of differential amplifier 102 and output transistor 101 is higher than 0 dB), then the lowered voltage power supply circuit shown in FIG. 1 oscillates. The relationship between the total gain and the phase with respect to a variation of the frequency is indicated by a Bode diagram shown in FIG. 6.
As seen from FIG. 6, when total gain G.sub.01 +G.sub.02 of differential amplifier 102 and output transistor 101 is equal to 0 dB (gain=1 time), if phase .phi. (sum value of .phi.1 of differential amplifier 102 and .phi.2 of output transistor 101) of output signal V.sub.INT with respect to input signal IN is delayed with respect to -180 degrees, then the lowered voltage power supply circuit oscillates, but if it is advanced with respect to -180 degrees, then the lowered voltage power supply circuit does not oscillate. The difference between the phase when total gain G.sub.01 +G.sub.02 is equal to 0 dB and -180 degrees is called phase margin .DELTA..phi., and generally, as phase margin .DELTA..phi. increases, the liability of oscillation of the circuit increases.
In order to increase phase margin .DELTA..phi., the difference between cutoff frequency (frequency with which the gain decreases 3 dB) .omega..sub.P1 of differential amplifier 102 and cutoff frequency .omega..sub.P2 Of output transistor 101 should be increased. In the lowered voltage power supply circuit shown in FIG. 1, either cutoff frequency .omega..sub.P2 of output transistor 101 should be lowered to lower the gain at a high frequency, or cutoff frequency .omega..sub.P1 of differential amplifier 102 should be raised to increase the response speed.
Usually, to lower the cutoff frequency can be realized more simply than to raise the cutoff frequency. In the conventional lowered voltage power supply circuit, phase compensating capacitor 104 of a large capacity is provided on the output side to lower cutoff frequency .omega..sub.P2 of output transistor 101 to increase phase margin .DELTA..phi. to prevent oscillation of the circuit.
However, an increase of the capacitance of phase compensating capacitor 104 results in necessity for a greater area to lay out circuit elements. Therefore, it is difficult to adopt the construction described above for semiconductor integrated circuits in recent years for which the demand for higher integration is progressively increasing.